The present invention relates to adaptive power supply voltage regulation for programmable logic, and more particularly, to techniques for providing regulated power supply voltages to programmable logic integrated circuits that can be adapted to compensate for process and temperature variations, or other factors.
Programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) typically receive a power supply voltage (VCC) from an external voltage regulator. The voltage regulator provides a fixed regulated voltage that is based on a target value. The power supply voltage is distributed to circuits inside the PLD/FPGA.
Process variations effect the speed and power consumption of transistors in a PLD significantly. For example, when hundreds of PLDs are mass produced according to a particular semiconductor process, the goal is for all of the a PLDs to be identical. In reality, transistors in some of the PLDs end up having shorter gate lengths than the transistors in other PLDs because of variations in the process.
The PLDs that have short gate length transistors operate faster than the PLDs that have longer gate length transistors. The faster chips consume more power than the slower chips. Typically, PLD chips are grouped into bins after manufacture based on their individual speed and power consumption characteristics. A customer can then select a PLD with particular speed and power requirements from one of the bins.
However, customer demand sometimes does not match the bin distribution of the PLDs. For example, a manufacturing process may generate a larger number of slow speed PLDs than customers want to purchase. Also, a customer has no way of controlling the speed and power consumption of a particular PLD.
Because the external voltage regulator generates fixed supply voltages, the supply voltages cannot be used to optimize the speed or power of an individual PLD. Therefore, some PLD die may have to be discarded if their speed parameters and power consumption is outside predefined limits. The contribution of current leakage adds an additional criteria to power consumption on a PLD. Also, process variations are excepted to become more significant as transistor sizes are scaled down further.
Therefore, it would be desirable to provide techniques for providing regulated power supply voltages to programmable logic integrated circuits that can be adapted to compensate for process and temperature variations, or factors.